Renesas PCA7429G02 Información técnica descargar pdf (Pagina 62)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37272M6/M8–XXXSP/FP, M37272MA–XXXSP

M37272E8SP/FP, M37272EFSP

MITSUBISHI MICROCOMPUTERS

Rev. 1.3

Fig. 8.10.12 Sync Pulse Counter Register

8.10.13 Synchronous Signal Counter

The synchronous signal counter counts the composite sync signal

taken out from a video signal in the data slicer circuit or the vertical

synchronous signal Vsep as a count source.

The count value in a certain time (T time) generated by f(XIN)/2

f(XIN)/2

is stored into the 5-bit latch. Accordingly, the latch value

changes in the cycle of T time. When the count value exceeds “1F16,”

“1F16” is stored into the latch.

Fig. 8.10.13 Synchronous Signal Counter Block Diagram

The latch value can be obtained by reading out the sync pulse counter

sync pulse counter register.

The synchronous signal counter is used when bit 0 of PWM mode

Figure 8.10.12 shows the structure of the sync pulse counter and

Figure 8.10.13 shows the synchronous signal counter block diagram.

b7 b6 b5 b4 b3 b2 b1 b0

Sync pulse counter register (HC) [Address 00E9

]

Sync Pulse Counter Register

0R—

6, 7 0 R —

Count value (HC0 to HC4)

0RWCount source (HC5) 0: H

SYNC

signal

1: Composite sync signal

B After resetFunctionsName

Nothing is assigned. These bits are write disable bits.

When these bits are read out, the values are “0.”

Reset

5-bit counter

Latch (5 bits)

f(X

)/2

Composite

sync signal

SYNC

signal

Counter

Sync pulse

counter register

Data bus

Selection gate : connected to black

side when reset.

1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 144 145

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Renesas PCA7429G02 Información técnica Pagina 62

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