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Vcc1 = Vcc2 = 3 V

(3) Timing Requirements

Table 5.7 and Figures 5.6 show timing requirements in memory expansion mode and microprocessor

mode.

Table 5.7 Timing requirements

Figure 5.6 Timing requirements

* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.

Symbol

Item

Actual MCU

[ns]

This product

[ns]

Min. Max.Min. Max.

tsu(DB-RD)

tsu(RDY-BCLK)

tsu(HOLD-BCLK)

th(RD-DB)

th(BCLK-RDY)

th(BCLK-HOLD)

td(BCLK-HLDA)

Data input setup time

RDY* input setup time

HOLD* input setup time

Data input hold time

RDY* input hold time

HOLD* input hold time

HLDA* output delay time

See left

Common to "with wait" and "no-wait" (this product)

Common to "with wait" and "no-wait" (actual MCU)

See left

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Renesas M3062PT-EPB Información técnica Pagina 64