
APPLICATION NOTE
REJ05B0582-0200/Rev.2.00 May 2007 Page 1 of 6
4514 Group, 4519 Group
Differences between 4514 Group and 4519 Group
1. Differences between 4514 Group and 4519 Group
Parameter 4514 Group 4519 Group
CPU TABP instruction *1
Low-order 8 bits of 10 bits data in ROM
can be referred. (Register A,B)
All 10 bits data in ROM can be referred.
(Register A,B,D)
Minimum instruction execution time 0.75 μs(f(XIN)=4.0 MHz) 0.5 μs(f(XIN)=6.0 MHz)
I/O port D *2
N-channel open-drain output
Input voltage : V
SS to 12 V
N-channel open-drain output / CMOS
output selectable
Input voltage : V
SS to VDD
P0 N-channel open-drain output
N-channel open-drain output / CMOS
output selectable
P1 N-channel open-drain output
N-channel open-drain output / CMOS
output selectable
P2 Input port I/O port
P5 CMOS output
N-channel open-drain output / CMOS
output selectable
P6 -
P6 can be also used as analog input
pins.
P0, P1 pull-up transistor control 2-port unit 1 port unit
*3 Input control of INT0 and INT1 - Available
Timer Prescaler Prescaler(divided by 4/divided by 16) 8-bit programmable timer
Timer 1 Count source ORCLK INSTCK, ORCLK, XIN, CNTR0
Timer 1 count auto-stop circuit - Available
Period measurement function - Available
pulse width measurement function
Timer 2 Count source *4 T1UDF, ORCLK, CNTR0, WDTUDF T1UDF, ORCLK, STCK, PWMOUT
Timer 3 Count source T2UDF, ORCLK T2UDF, ORCLK, CNTR1, PWMOUT
Timer 3 count auto-stop circuit - Available
PWM output function - Available
Timer 4 Count source *5 T3UDF, ORCLK, CNTR1 ORCLK/2, XIN
Reload register *6 1 (R4) 2(R4L, R4H)
PWM output function - Available
CNTR0 input
Timer 2 count source
(Rising edge)
Timer 1 count source
(Rising edge / falling edge selectable)
CNTR0 output
T1UDF/2
AND signal of T1UDF/2 and T2UDF/2
T1UDF/2
T2UDF/2
CNTR1 input
Timer 4 count source
(Rising edge)
Timer 3 count source
(Rising edge / falling edge selectable)
CNTR1 output
T3UDF/2
AND signal of T3UDF/2 and T4UDF/2
PWM output (Timer 4)
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