Renesas Emulation Pod M3062NT3-RPD-E Manual de usuario descargar pdf (Pagina 2)

REJ05B0185-0201Z/Rev.2.01 August 2004 Page 2 of 10

M16C/62P, M16C/62N Group

Differences between M16C/62P and M16C/62N

Table 3.1.2 Function differences (mask ROM version and flash memory version)-2(Note1)

Note 1: About the details and the characteristics, refer to hardware manual.

Note 2: I

C is a trademark of Philips Semiconductors Corporation.

Note 3: IEBus is a trademark of NEC Electronics Corporation.

Table 3.1.2 Function differences (flash memory version)(Note1)

Note 1: About the details and the characteristics, refer to hardware manual.

Item M16C/62P M16C/62N

Watchdog timer Count source protective mode is available

No count source protective mode

Address match interrupt 4 2

Timers A, timer B

Count source

Selectable: f1, f2, f8, f32, fC32

Selectable: f1, f8, f32, fC32

Timer A two-phase pulse

signal processing

Function Z-phase (counter reset) input No function Z-phase (counter reset) input

Timer functions for

three-phase motor control

Function protect by protect register

Count source is selected f1, f2, f8, f32, fC32

Dead time timer count source is selected: f1, f1

divided by 2, f2, f2 divided by 2

Three-phase output forcible shutoff function

based on NMI input is available, output polarity

change, carrier wave phase detection

No function protected by protect register

Count source is selected :f1, f8, f32, fC32

Dead time timer count source is fixed at f1

divided by 2

Serial I/O

(UART0 to UART2)

(UART, Clock synchronous, I

C-bus

(Note 2),

IEBus

(Note 3)) x 3

(UART, Clock synchronous) x 2

(UART, Clock synchronous, I

C-bus

(Note 2),

IEBus

(Note 3)) x 1

UART0 to UART2,

SI/O3, SI/O4

Count source

Select from f1SIO, f2SIO, f8SIO, f32SIO Select from f1, f8, f32

Serial I/O

RTS timing

Assert low when receive buffer is read Assert low when reception is completed

UART0 to UART2

Overrun error occur timing

This error occurs if the serial I/O started receiving

the next data before reading the UiRB register

(i=0 to 2) and received the 7th bit of the next data

(Clock synchronous).

This error occurs if the serial I/O started receiving

the next data before reading the UiRB register

and received the bit one before the last stop bit of

the next data (UART).

This error occurs when the next data is ready

before contents of UiRB register (i=0 to 2) are

read out

Serial I/O

CTS/RTS separate function

Have None

UART2 data transmit timing After data was written, transfer starts at the 2nd

BRG overflow timing (same as UART0 and

UART1)

After data was written, transfer starts at the 1st

BRG overflow timing (Output starts one cycle of

BRG overflow earlier than UART0 and UART1)

Serial I/O

Sleep function

None Have

Serial I/O

C mode

Start condition, stop condition: Auto-generation

Start condition, stop condition:

Not auto-generation

Serial I/O

C mode

SDA delay

SDA digital delay count source: BRG SDA digital delay count source: 1/f(XIN)

SI/O3, SI/O4

Clock polarity

Selectable

Fixed

A/D converter

10 bits x 8 channels

Expandable up to 26 channels

10 bits x 8 channels

Expandable up to 18 channels

A/D converter operation

clock

Selectable: fAD, fAD divided by 2, 3, 4, 6, 12 Selectable: fAD, fAD/2, fAD/4

A/D converter input pin Select from ports P0, P2, P10 Select from ports P0, P10

Item M16C/62P M16C/62N

User ROM blocks 14 blocks: 4 Kbytes X 3, 8 Kbytes X 3,

32 Kbytes X 1, 64 Kbytes X 7

(Flash memory: max. 512 Kbytes)

7 blocks: 4 Kbytes X 2, 24 Kbytes X 1,

32 Kbytes X 1, 64 Kbytes X 3

(Flash memory: max. 256 Kbytes)

CPU rewrite mode EW1 mode is available No EW1 mode

1 2 3 4 5 6 7 8 9 10

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