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E8a Emulator Section 6 Notes on Using the E8a Emulator

26. DMAC during a user program halt

When the user program is halted or when the memory is referred to or modified during user program execution,

DMA transfer is disabled. In such cases, the E8a emulator sets the registers below as following. Therefore, if you

refer to the registers below in the memory window, etc., it shows that DMA is disabled.

- DMA0 Control Register (DM0CON)

DMA enable bit (bit 3) 0: DMA disabled

- DMA1 Control Register (DM1CON)

DMA enable bit (bit 3) 0: DMA disabled

- Interrupt Control Register

Interrupt request bit (bit 3) 0: Interrupt not requested [*1]

Do not enable DMA transfer from the memory window, etc., but enable it in the user program.

Note

[*1] When restarting the user program, though the E8a emulator sets back the value of a DMA enable bit to the

previous value that was set before the program stops, the interrupt request bit remains 0.

REJ10J1640-0400

Rev.4.00 Page 21 of 31

Apr 30, 2010

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Renesas M16C/6NN Manual de usuario Pagina 24