Renesas V850 Series Manual de usuario descargar pdf (Pagina 20)

V850 Debugger and Trace 2 0 G e n e r a l S y s t e m S e t t i n g s

SYStem.JtagClock JTAG clock selection

Default frequency: 1 MHz.

Selects the JTAG port frequency (TCK). Any frequency up to 25 MHz can be entered, it will be generated by

the debuggers internal PLL.

For CPUs which come up with very low clock speeds it might be necessary to slow down the JTAG

frequency. After initialization of the CPUs PLL the JTAG clock can be increased.

SYStem.LOCK Lock and tristate the debug port

Default: OFF.

If the system is locked, no access to the debug port will be performed by the debugger. While locked, the

debug connector of the debugger is tristated. The main intention of the lock command is to give debug

access to another tool.

Format: SYStem.JtagClock [<frequency>]

SYStem.BdmClock [<frequency>] (deprecated).

If there are buffers, additional loads or high capacities on the JTAG/COP lines,

reduce the debug speed.

Format: SYStem.LOCK [ON | OFF]

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Renesas V850 Series Manual de usuario Pagina 20