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V850E2/MN4 A/D Converter Control

R01AN0923EJ0100 Rev.1.00 Page 13 of 26

Feb 13, 2012

4.2.5 A/D Converter Interrupt Control Register i (ADCAnIOCi)

The A/D conversion end interrupt INTADCAnTi can be generated when the A/D conversion of a certain channel has

been completed.

This register specifies the channels for which the interrupt INTADCAnTi is generated on the completion of A/D

conversion.

If ADCAnIOCi is cleared to 0000 0000H, the interrupt INTADCAnTi is automatically generated on the completion of

A/D conversion of CGi.

Figure 4.8 ADCAnIOCi Register Format

Setting example

ADCA0IOC0 = 0x00000001; /* ADCATINT0 does not output at the end of channel diag conversion;

ADCATINT0 output at the end of channel 00 (CG0) conversion */

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Renesas MN4 Manual de usuario Pagina 13