20
3851 Group
(Built-in 16 KB ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
Table 4 Multi-master I
2
C-BUS interface functions
Item
Format
Communication mode
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Figure 19 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 4 lists the multi-master I
2
C-BUS interface
functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address
register, the I
2
C data shift register, the I
2
C clock control register,
the I
2
C control register, the I
2
C status register, the I
2
C start/stop
condition control register and other control circuits.
When using the multi-master I
2
C-BUS interface, set 1 MHz or
more to φ.
Note: Mitsubishi Electric Corporation assumes no responsibility for in-
fringement of any third-party’s rights or originating in the use of the
connection control function between the I
2
C-BUS interface and the
ports SCL
1, SCL2, SDA1 and SDA2 with the bit 6 of I
2
C control regis-
ter (002E
16).
Fig. 19 Block diagram of multi-master I
2
C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
SCL clock frequency
I
2
C address registerb7 b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1
S
A
D
0
RWB
N
o
i
s
e
e
l
i
m
i
n
a
t
i
o
n
c
i
r
c
u
i
t
Address comparator
b7
I
2
C data shift register
b0
Data
control
circuit
System clock (φ)
Interrupt
generating
circuit
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
s
g
n
a
(
I
I
C
I
R
Q
)
b
7
0
b
0
S
1
b
7b
0
T
I
S
1
0
B
I
T
S
A
D
A
L
B
C
2B
C
1B
C
0
S
1
D
t
c
o
u
n
t
e
B
B
c
i
r
c
u
i
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
Noise
elimination
circuit
b
7b
0
A
C
A
C
K
B
I
T
FAST
MODE
C
C
R
4CCR
CCR
C
C
R
1CCR
nterna
ata
us
o
c
v
s
o
n
0
S2
S0D
AL
circuit
ES0
I
2
C start/stop condition
control registe
SSC
S
S
C
S
S
C
S
S
C
1S
S
C
I
2
C clock control register
I
2
C status register
S2D
CLK
STP
I
2
C clock control registe
S1D I C control register
S
e
r
i
a
l
d
a
t
a
(
S
D
A)
S
e
r
i
a
l
c
l
o
c
k
(
S
C
L)
(88 paginas)
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