20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
TIMERS
The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and
timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2,
and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding timer
latch is reloaded into the timer and the count is continued. When a
timer underflows, the interrupt request bit corresponding to that timer
is set to “1”.
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
Fig. 16 Timer block diagram
“
1
0
”
Timer Y stop
control bit
Falling edge detection
Period measure-
ment mode
Timer Y interrupt
request
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Rising edge detection
“00”,“01”,“11”
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Timer X (low) (8) T
i
m
e
r
X
(
h
i
g
h
)
(
8
)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)
Q
Q
T
S
“0”
“
1
”
“10”
f
(
XI
N)
/
1
6
(
f
(
X
C
I
N)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
✽
)
“00”,“01”,“11”
C
N
T
R0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
C
N
T
R0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
B
u
z
z
e
r
o
u
t
p
u
t
m
o
d
e
Timer 2 latch (8)
T
i
m
e
r
2
(
8
)
“
1
”
“
1
”
f
(
X
C
I
N
)
/
3
2
Timer 1 interrupt
request
D
a
t
a
b
u
s
✽
I
n
t
e
r
n
a
l
c
l
o
c
k
φ
=
X
C
I
N
d
i
v
i
d
e
d
b
y
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
C
N
T
R
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
CNTR
1
interrupt
request
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
“
0
0
”
,
“
0
1
”
,
“
1
0
”
“11”
“
0
0
”
,
“
1
1
”
“
0
1
”
Timer X operating
mode bits
P4
3
/CNTR
1
/BEEP-
P
4
2
/
C
N
T
R
0
/
B
E
E
P
+
“
0
”
“
1
”
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Buzzer output mode
P
4
2
l
a
t
c
h
P
42
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
B
E
E
P
-
v
a
l
i
d
b
i
t
f(X
CIN
)
“
0
”
“
1
”
f(X
IN
)
Timer X count source
selection bit
f(X
CIN
)/32
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
Timer X stop control bit
Timer X write control bit
T
i
m
e
r
X
(
h
i
g
h
)
l
a
t
c
h
(
8
)
CNTR1 active
edge switch bit
P
4
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P4
3 latch
f(X
IN)/16
(f(X
CIN)/16 in low-speed mode
✽
)
“1”
“
0
”
Timer Y (low) (8) Timer Y (high) (8)
Timer Y (low) latch (8) Timer Y (low) high (8)
f(XIN)/16
(f(X
CIN)/16 in low-speed mode
✽
)
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Timer 2 interrupt
request
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
f
(
XI
N)
/
1
6
(
f
(
X
C
I
N)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
✽
)
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Timer 3 latch (8)
T
i
m
e
r
3
(
8
)
“
0
”
“0”
Timer 1 latch (8)
T
i
m
e
r
1
(
8
)
“
1
”
“0”
Timer 3 count source
selection bit
(11 paginas)
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