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SH7285 Group

Example of Initialization

REJ06B0860-0100/Rev.1.00 June 2009 Page 2 of 21

1. Introduction

1.1 Specifications

Configure the clock pulse generator (CPG) after the reset is canceled.

1.2 Modules Used

• Clock pulse generator (CPG)

1.3 Applicable Conditions

MCU SH7285

Operating Frequency Internal clock: 100 MHz

Bus clock: 50 MHz

Peripheral clock: 50 MHz

Integrated Development

Environment

Renesas Technology Corp.

High-performance Embedded Workshop Ver.4.04.01

C compiler Renesas Technology SuperH RISC engine Family

C/C++ compiler package Ver.9.01 Release 01

Compiler options Default setting in the High-performance Embedded Workshop

(-cpu=sh2 -debug -gbr=auto -global_volatile=0 -opt_range=all

-infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1)

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