Renesas H8S/2655 Series Especificaciones descargar pdf (Pagina 14)

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As one of the key reasons for using the

H8S and H8/300H is the 16MBytes

linear address space, it will often be used

in a system with a large amount of

external memory. Consequently, H8S

and H8/300H are supported by a

powerful bus state controller (BSC) that

allows external memory and/or

peripherals to be connected with no (in

some rare cases with little) glue logic.

Also, the BSC helps to get the maximum

performance out of any external devices,

for example by avoiding address decode

delays, where on-chip chip-select

generation is used.

The BSC divides the memory space into

8 areas. For each of these areas a number

of attributes is selectable,for example:

• the wait mode (automatic insertion or

hardware protocol)

• the number of wait states

• the bus width (8/16-bit)

• DRAM access protocol for one area

on 300H (=2Mbytes) and for 4 areas

on H8S (=8Mbytes)(not on all

devices)

Bus State Controller

(BSC) on H8S

One of the major advantages of H8S over

H8/300H is its basic instruction

execution within a single clock cycle, that

is only 50ns at 20MHz clock if executed

from internal memory. In order to

minimise the negative impact on

performance when going off chip, every

effort has been made to create a BSC

with a maximum of throughput and

ﬂexibility.

Major enhancements include support for

fast-page mode DRAM (on H8S/26xx

and on some H8S/23xx derivatives),

burst mode ROM, a write buffer that

Bus State Controller (BSC)

Address bus

Ø

Data Bus

tACC

Improved Access Time

Address bus

Ø

Data Bus

tACC

executes slow external write accesses

independently (on H8S/26xx and on

some H8S/23xx derivatives) and the

improvement of read access time by

moving the clock edge that latches the

read data to the end of the bus cycle.

DRAM interface

Areas two to ﬁve can be set to interface

directly to DRAM on on H8S/26xx and

on some H8S/23xx derivatives,allowing

up to 8MB of DRAM to be connected

without any glue logic. The BSC

handles the address multiplexing (8,9 or

10 bits),the timing and allows to use fast

page mode. DRAM with CAS-before-

RAS (CBR) or self-refresh are

supported. For CBR refresh mode the

BSC provides an independent refresh

counter,so that no other timers have to

be used.

Figure 10

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