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PD70F3003A, 70F3025A, 70F3003A(A)

Data Sheet U13189EJ5V1DS

(9) CSI timing (2/2)

(ii) CSI3 timing

Parameter Symbol Conditions MIN. MAX. Unit

SCK3 cycle <67> tCYSK4 Input 500 ns

SCK3 high-level width <68> tWSKH4 Input 180 ns

SCK3 low-level width <69> tWSKL4 Input 180 ns

SI3 setup time (to SCK3↑) <70> tSSISK4 100 ns

SI3 hold time (from SCK3↑) <71> tHSKSI4 50 ns

SO3 output delay time (from SCK3↓)

<72> tDSKSO4 RL = 1.5 kΩ 150 ns

SO3 output hold time (from SCK3↑)

<73> tHSKSO4 CL = 50 pF tWSKH4 ns

Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output

lines.

SCKn (I/O)

SIn (input)

SOn (output)

< 67 >

< 69 >

< 68 >

< 70 >

< 71 >

< 72 >

< 73 >

Input data

Output data

Remark 1. The broken line indicates the high-impedance state.

2. n = 0 to 3

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 48 49

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