Renesas CPU Board M3A-HS19 Información técnica descargar pdf (Pagina 14)

Overview

1.7 M3A-HS19 Memory Mapping

Rev.1.01 Oct 28, 2008 1-8

REJ10J1351-0101

1.7 M3A-HS19 Memory Mapping

Area 0 bus width: (Default) MD3 = 0 •••16-bit

Data alignment: (SW4-1) MD5 = 0(ON) •••Big endian

MD5 = 1(OFF) •••Little endian

Figure 1.7.1 show the memory mapping examples of the SH7619 on the M3A-HS19.

Logical Address [31~29] Area Cacheable/Non-cacheable

000~011 P0 Cacheable

100~ P1 Cacheable

101~ P2 Non cacheable

110~ P3 Cacheable

111~ P4 Non-cacheable (on-chip I/O) etc.

(P0 and shadow area (P1, P2, P3))

Address [28~0] Area MAP = 0 MAP = 1

Flash Memory (4 MB)

H’0000 0000~H’003F FFFF

Flash Memory (4 MB)

H’0000 0000~H’003F FFFF

H'0000 0000

Area 0

64 MB

User Area

H'0400 0000

Area 1

64 MB

Reserved *

(Do not use)

Reserved *

(Do not use)

H'0800 0000

Area 2

64 MB

Reserved *

(Do not use)

Reserved *

(Do not use)

SDRAM (16 MB)

H’0C00 0000~H’0CFF FFFF

SDRAM (16 MB)

H’0C00 0000~H’0CFF FFFF

H'0C00 0000

Area 3

64 MB

User Area

H'1000 0000

Area 4

64 MB

User Area User Area

H'1400 0000

Area 5A

32 MB

Reserved

(Do not use)

H'1600 0000

Area 5B

32 MB

User Area

PCMCIA

H'1800 0000

Area 6A

32 MB

Reserved

(Do not use)

H'1A00 0000

Area 6B

32 MB

User Area

PCMCIA

H'1C00 0000

H'1FFF FFFF

Area 7

64 MB

Reserved *

(Do not use)

Reserved

(Do not use)

Note: H'0000 0000 to H'1FFF FFFF are the cache-enabled area.

Figure 1.7.1 SH7619 Memory Mapping Examples

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 73 74

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Renesas CPU Board M3A-HS19 Información técnica Pagina 14

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