Renesas CPU Board M3A-HS19 Información técnica descargar pdf (Pagina 27)

Features and Specifications

2.3.4 External EEPROM

Rev.1.01

Oct 28, .2008 2-11

REJ10J1351-0101

2.3.4 External EEPROM

The M3A-HS19 is provided with an EEPROM for storing MAC address.

Access to the EEPROM is enabled by using the SH7261 I/O ports (PC03, PC02, PC01 and PC00). A MAC address

consists of 48-bit numbers.

Table 2.3.6 lists instruction sets, and Figure 2.3.6 shows the block diagram of CPU and EEPROM connection.

Figure 2.3.7 shows the EEPROM-AC timing and Figure 2.3.8 shows EEPROM-read/write timing.

Settings for following instruction sets are not required;

- A7 to A0 for WRAL, ERAL, EWEN, and EWDS instructions

- Data for ERASE, ERAL, EWEN and EWDS instructions

Table 2.3.6 Instruction Sets (S-93C76AFT)

Start Bit Operation

Code

Address Data

Command

1 2 3 4 5 6~13 14~29

READ 1 1 0 - A8 A7~A0 D15~D0 (OUT)

WRITE 1 0 1 - A8 A7~A0 D15~D0 (IN)

ERASE 1 1 1 - A8 A7~A0 -

WRAL 1 0 0 0 1 - D15~D0(IN)

ERAL 1 0 0 1 0 - -

EWEN 1 0 0 1 1 - -

EWDS 1 0 0 0 0 - -

Figure 2.3.6 CPU and EEPROM Connection

S-93C76AFT(U4)

PC03/MII_RXD3

SH7619 (U1)

SKPC02/MII_RXD2

PC01/MII_RXD1

PC00/MII_RXD0

EEPROM

DO GND

TEST

Vcc

3.3 V

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 73 74

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Renesas CPU Board M3A-HS19 Información técnica Pagina 27