REJ05B0591-0111/Rev.1.11 January 2007 Page 2 of 8
M16C/30P, M16C/30 Group
Differences between M16C/30P and M16C/30
Table 3.1.2 Function Differences (2) (Note1)
Item M16C/30P M16C/30
Serial Interface
(UART0 to UART2)
(UART, Clock synchronous, I
2
C bus
(2)
) x 2
(UART, Clock synchronous, I
2
C bus
(2)
, IEBus
(3)
)
x 1
(UART, Clock synchronous) x 2
(UART, Clock synchronous, I
2
C bus
(2)
, IEBus
(3)
)
x 1
UART0 to UART2
Count Source
Select from f1SIO, f2SIO, f8SIO, f32SIO Select from f1, f8, f32
Serial Interface
RTS
Timing
Assert low when receive buffer is read Assert low when reception is completed
UART0 to UART2
Overrun Error
Generation Timing
This error occurs if the serial interface started
receiving the next data before reading the UiRB
register (i=0 to 2) and received the 7th bit of the
next data (clock synchronous)
This error occurs if the serial interface started
receiving the next data before reading the UiRB
register and received the bit one before the last
stop bit of the next data (UART)
This error occurs when the next data is ready
before contents of UARTi receive buffer register
are read out.
Serial Interface
CTS
/RTS Separate
Function
Built-in None
UART2 Data Transmit
Timing
After data was written, transfer starts at the 2nd
BRG overflow timing
(same as UART0 and UART1)
After data was written, transfer starts at the 1st
BRG overflow timing
(output starts one cycle of BRG overflow earlier
than UART0 and UART1)
Serial Interface
Sleep Function
None Built-in
Serial Interface
I
2
C Mode
Start condition, stop condition:
Auto-generationable
Start condition, stop condition:
Not auto-generationable
Serial Interface
I
2
C Mode SDA Delay
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Analog or digital delay is selected as SDA delay
SDA digital delay count source: 1/f(XIN)
A/D Converter 10 bits x 8 channels
Expandable up to 18 channels
10 bits x 8 channels
Expandable up to 10 channels
A/D Converter
Operation Clock
Select from fAD, fAD divided by 2, 3, 4, 6, 12 Select from fAD, fAD/2, fAD/4
A/D Converter
Operation Mode
One-shot mode, Repeat mode One-shot mode
A/D Converter
Input Pin
Select from Ports P0, P10 Fixed at Port P10
CRC Calculation
Built-in None
Package
100P6Q-A, 100P6S-A 100P6Q-A, 100P6S-A
NOTES:
1. About the details and the characteristics, refer to hardware manual.
2. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
3. IEBus is a registered trademark of NEC Electronics Corporation.
(74 paginas)
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