Renesas R8C/15 Manual de usuario descargar pdf (Pagina 10)

Rev.0.10 Mar 4, 2004 Page 10 of 16

REJ03B0078-0010Z

Under development

R8C/15 Group 2. Central Processing Unit (CPU)

Preliminary specification

Specications in this manual are tentative and subject to change.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I

flag is cleared to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.

The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for

software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from

level 0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write “0”. When read, its content is indeterminate.

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Renesas R8C/15 Manual de usuario Pagina 10