Renesas Single-Chip Microcomputer M38C89T-ADF Manual de usuario descargar pdf (Pagina 23)

Library Reference

32BClock Pulse Generator

R_CPG_Set

4.2.1

Rev.1.00 May 22 2012

REJ09B0566

4-3

Synopsis

Prototype

4.2.1. Clock Pulse Generator

R_CPG_Set

Configure the clock pulse generator

bool R_CPG_Set (

uint32_t data1, // Input frequency uint32_t

data2, // System clock frequency uint32_t

data3, // Peripheral clock frequency uint8_t

data4, // Clock mode settings uint8_t data5

// Configuration options

);

Description

Set the clock output frequencies and options.

[data1]

The frequency of the main clock oscillator in Hertz.

[data2]

The desired frequency of the System clock (ICLK) in Hertz.

[data3]

The desired frequency of the Peripheral clock (PCLK) in Hertz.

[data4]

Select the clock source

To select the Clock Source,

PDL_CPG_CK_0

PDL_CPG_USB_EXT

PDL_CPG_CK_2

PDL_CPG_USB_PLL

Note: The default setting is shown in bold.

[data5]

Configuration options.

Specifies the clock operating mode (Mode 0 to 3)

• BCLK pin output control

PDL_CPG_OUT_CK_00

PDL_CPG_OUT_CK_01

PDL_CPG_OUT_CK_02

PDL_CPG_OUT_CK_HIZ

Select whether to enable or disable the CKIO output

PDL_CPG_CK2_ENABLE

PDL_CPG_CK2_DISABLE

Enables or disables CKOEN2 bit in FRQCR register

Note: The default setting is shown in bold.

Return value True if all parameters are valid and exclusive; otherwise false.

For SH7267, the following rules shall be checked:

•

Main clock oscillator frequency: 10 to 18 MHz.

•

ICLK

: 40 to 144 MHz

•

PCLK

: 6.7 to 36 MHz

•

BCLK

: 40 to 72 MHz

•

ICLK

≥ f

PCLK

and f

ICLK

≥ f

BCLK

Functionality

Clock pulse generator

References

None.

Remarks • This function must be called before configuring clock-dependent modules.

• This function modifies the BCLK pin for input or output.

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