Renesas User System Interface Cable HS36049ECH61H Manual de usuario descargar pdf (Pagina 10)

■ Controller Area Network (RCAN-ET)

• Supports CAN specification 2.0B

• Bit timing compliant with ISO-11898-1

• 16 Mailbox version

• 15 programmable Mailboxes for transmit/receive

+ 1 receive-only Mailbox

• Sleep mode for low power consumption and automatic

recovery from sleep mode by detecting CAN bus activity

• Programmable receive filter mask (standard and

extended identifier) supported by all Mailboxes

• Programmable CAN data rate up to 1MBit/s

• Transmit message queuing with internal priority

sorting mechanism

■ Universal Serial Bus

• Provides v2.0 support

• Offers full-speed, 12Mbps

communication

• Bus-powered mode or

self-powered

• Up to 9 endpoints can be specified

• Four transfer modes supported:

Control, Interrupt, Bulk,

and Isochronous

• On-chip bus transceiver with

option for using external transceiver

• Total 1280-Byte FIFO buffer

Peripherals

8

H8

®

Family — On-chip Peripherals: Communication I/F

E-DMAC

Internal bus interface

Internal bus

RAM

Transmit

descriptor

Receive

descriptor

Descriptor

information

Transmit

DMAC

Descriptor

information

Receive

DMAC

Tran smit

buffer

Receive

buffer

Tran smit

FIFO

Receive

FIFO

MAC

Converter

MII/RMII conversion

PORT

PHY

Transmit

controller

Receive

controller

MII

Command

status

interface

Microprocessor

Interface

MCR IRR

GSR

IMR

Mailbox 0 to 15

(register)

Mailbox 0 to 15

(RAM)

Mailbox Control

32-bit internal bus system

16-bit

peripheral

bus

CAN interface

Control

signals

Status

signals

CAN Core

TEC

REC

BCR Transmit Buffer Receive Buffer

RCAN-ET Architecture

USB Block Diagram: H8S/2215R

Registers

Interface

Internal

transceiver

[Connection/disconnection]

[Data]

[Internal bus]

[System clock]

[USB operating clock]

[Interrupt request signal]

[Power mode selection]

[Power supply]

Peripheral data bus

Peripheral address bus

Peripheral bus

control signal

(12MHz)

(48MHz)

(48MHz)

(16MHz)

EXTAL48

XTAL48

VBUS

[Suspend]

DrVss

Rs

Rs

DrVcc

UDC core

USD+

USD-

D+

D-

PLL circuit

(x3)

USB clock

generator

1280-Byte FIFO

EP3i

EP3o

EP0o

EP1i

EP2i

EP2o

EP5iEP4i

EP4o

EP0s

EP0i

UDC synchronization

circuit

USPND

UDC:

USB Device Controller

EP0s:

Endpoint 0 setup FIFO

EP0i to 5i:

Endpoint 0 to 5 In FIFO

EP0o to 4o:

Endpoint 0 to 4 Out FIFO

Legend:

IRQ6

EXIRQ0, EXIRQ1

DREQ0, DREQ1

UBPM

USB

φ

[DMA internal request signal]

Ethernet Hardware

MAC 100/10

Block Diagram

■ Ethernet Hardware MAC 100/10

• Transmission and reception of

Ethernet/IEEE802.3 frames

• Supports 10/100 Mbps receive/transfer

• Supports full-duplex and half-duplex modes

• Conforms to IEEE802.3u standard MII

(Media Independent Interface)

•Magic Packet detection and

Wake-On-LAN (WOL) signal output

• Conforms to IEEE802.3x flow control

• Dedicated E-DMAC (DMA Controller)

• Transmit/receive frame status information

is indicated in descriptors

• Achieves efficient system bus utilization

through use of block transfer (16-byte units)

• Supports single-frame/multi-buffer operation

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