Renesas PROM Programming Adapter PCA7408 Manual de usuario Pagina 60
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- MARCADORES
Valorado. / 5. Basado en revisión del cliente
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 60 of 110
REJ03B0134-0100Z
Fig. 8.11.6 Vertical Position Register i
The vertical display start position for each block can be set in 512
steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to
“7F
16” in vertical position register i (i = 1 and 2) (addresses 00E116
and 00E216) The vertical position register i is shown in Figure 8.11.6.
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E1
16,
00E2
16
]
B Name Functions After reset R
W
Vertical Position Register i
0
to
6
7
Vertical display start positions
128 steps (00
16
to 7F
16
)
Indeterminate
0
(CVi : CVi0 to CVi6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
RW
R—
- 1. DESCRIPTION 0
- 2. FEATURES 0
- 3. APPLICATION 0
- REJ03B0134-0100Z 1
- Address 00E016 2
- Addresses 00DE16 and 00DF16 2
- Addresses 00E116 and 00E216 3
- Address 00E416 3
- Addresses 00E616 to 00E916 4
- Address 00E516 4
- Address 00EA16 5
- Addresses 00EC16 5
- Address 00ED16 6
- Addresses 00EE16 6
- Address 00EF16 7
- Addresses 00F416 7
- Address 00F516 8
- Addresses 00F916 8
- Address 00FB16 9
- Addresses 00FC16 9
- Address 00FD16 10
- Addresses 00FE16 10
- Address 00FF16 11
- Addresses 021B16 11
- 42P2R-A/E 13
- REVISION HISTORY 14
- RENESAS SALES OFFICES 15
- 8. FUNCTION BLOCK DESCRIPTION 16
- 8.1.1 CPU Mode Register 16
- RCR1 RCR0 21
- TABLE OF CONTENTS 24
- (4) Serial I/O interrupt 25
- (5) f(XIN)/4096 interrupt 25
- (6) Multi-master I 25
- C-BUS interface interrupt 25
- (7) BRK instruction interrupt 25
- 8.4 TIMERS 29
- 8.4.1 Timer 1 29
- 8.4.2 Timer 2 29
- 8.4.3 Timer 3 29
- 8.4.4 Timer 4 29
- Timer 34 Mode Register 30
- 8.5 SERIAL I/O 32
- 16), and the transfer 33
- OUT pin. Transfer 33
- 4. PIN CONFIGURATION 35
- Outline 42P4B 35
- Outline 42P2R-A/E 35
- 8.6 MULTI-MASTER I 37
- C-BUS INTERFACE 37
- C Data Shift Register 38
- C Address Register 39
- 16) is used to set ACK 40
- C Control Register 42
- (1) 7-bit addressing format 47
- (2) 10-bit addressing format 47
- (5) Writing to I 50
- C status register 50
- 8.8 A-D COMPARATOR 56
- 5. FUNCTIONAL BLOCK DIAGRAM 57
- 8.9 D-A CONVERTER 59
- 8.10 ROM CORRECTION FUNCTION 61
- 8.11 OSD FUNCTIONS 62
- OSD Control Register 65
- 8.11.1 Display Position 66
- 6. PERFORMANCE OVERVIEW 68
- Vertical Position Register i 69
- Horizontal Position Register 70
- 8.11.2 Character Size 71
- 8.11.3 Clock for OSD 73
- 8.11.4 Memory for OSD 74
- Border Selection Register 80
- 8.11.7 Multiline Display 81
- 8.11.8 OSD Output Pin Control 82
- 8.13. RESET CIRCUIT 85
- 8.14 CLOCK GENERATING CIRCUIT 86
- 8.17 ADDRESSING MODE 87
- 8.18 MACHINE INSTRUCTIONS 87
- 9. TECHNICAL NOTES 87
- 8.16 AUTO-CLEAR CIRCUIT 87
- 10. ABSOLUTE MAXIMUM RATINGS 88
- 7. PIN DESCRIPTION 90
- + Power source voltage 91
- 15. MULTI-MASTER I 92
- 16. PROM PROGRAMMING METHOD 93
- M37221EASP 95
- M37221EAFP 95
- 19. APPENDIX 96
- Pin Configuration (TOP VIEW) 96
- Memory Map 98
- Register (SFR) 100
- Program Counter at Reset 104
- Structure of Register 105
- Address 00C716 106
- Address 00CB16 107
- Address 00CD16 107
- Address 00D516 108
- Address 00D616 108
- Address 00D816 109
- Address 00D716 109
- Address 00D916 110
- Address 00DA16 110
- Address 00DB16 111
- Address 00DC16 111
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