MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
11
Fig. 4. Memory map of special function register 1 (SFR2) (2)
F0
16
F1
16
F2
16
F3
16
F4
16
F5
16
F6
16
F7
16
F8
16
F9
16
FA
16
FB
16
FC
16
FD
16
FE
16
FF
16
E0
16
E1
16
E2
16
E3
16
E4
16
E5
16
E6
16
E7
16
E8
16
E9
16
EB
16
EC
16
ED
16
EE
16
EF
16
EA
16
Data slicer control register 1 (DSC1)
Data register 3 (CD3)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (TM1)
Window register (WN)
Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)
Data register 1 (CD1)
Data register 2 (CD2)
Caption position register (CP)
Start bit position register (SP)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I
2
C
data shift register (S0)
I
2
C
control register (S1D)
I
2
C
clock control register (S2)
Interrupt request
register 1 (IREQ1)
Interrupt request
register 2 (IREQ2)
Interrupt control
register 1 (ICON1)
Interrupt control
register 2 (ICON2)
Clock run-in detect register 1 (CRD1)
Clock run-in detect register 2 (CRD2)
Data register 4 (CD4)
CPU mode
register (CPUM)
b7
b0
ADIN0ADIN1
ADVREF
ADSTR
ADV
TM20TM21TM22TM23TM24
TM10TM11TM12TM13TM14
CM2
TM1RTM2RTM3RTM4RCRTRVSCRADR
CK0
INT1R
DSRSIOR
TM1ETM2ETM3ETM4ECRTEVSCE
INT1EDSESIOEINT2E
TM25
b7
b0
CK0
00
16
?000?000
FF
16
07
16
FF
16
07
16
00000000
00000000
1
0
00 00 0 000
00 00 0 0
00
00 00 0 000
00 00 0 000
0 111 00
0 00 01 00 1
Sync slice register (SSL)
Data slicer control register 2 (DSC2)
I
2
C
status register (S1)
I
2
C
address register (S0D)
?
?
?
? 00 00 00 0
00
16
?
TM15TM16TM17
TM26TM27
?
SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW
LRBAD0AASALPINBBTRXMST
BC0BC1BC2ES0ALS
10 BIT
SAD
BSEL0BSEL1
CCR0CCR1CCR2CCR3CCR4
FAST
MODE
ACK
BIT
ACK
00
16
00
16
00
16
000001?0
1MSR
INT2R
IICRT56R
ADE
1MSE
IICET56ET56S
CM0CM1CM7 CM5CM6
DSC20DSC21DSC22DSC25DSC27
DSC10DSC11DSC12DSC15DSC17
0 00 00 01 1
SSL7
1 00 ?? ?? ?
CP0CP1CP2CP3CP4
SP0SP1SP2SP3SP4SP5SP6SP7
00
16
0 00 00 00 0
WN0WN1WN2WN3WN4WN5
CRD20CRD21CRD22CRD25CRD27 CRD25 CRD25 CRD25
1 00 11 1 10
CR21
CR11
0 10 10000
0 00 00 00 0
CRD10CRD11CRD12CRD15CRD17 CRD15 CRD15 CRD15
1
: “1” immediately after reset
: Fix this bit to “0” ( do not write “1”)
: Nothing is allocated
■SFR1 area (addresses E0
16
to FF
16
)
Address Register
: undefined immediately after reset
?
Bit allocation State immediately after reset
: Fix this bit to “1” ( do not write “0”)
0
: “0” immediately after reset
0
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