
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
82
Fig. 95. Clock generating circuit block diagram
X
CIN
X
COUT
OSC1 oscillating mode
selection bits
(Notes 1, 4)
Internal system clock
selection bit (Notes 1, 3)
Internal system clock
selection bit (Notes 1, 3)
Main clock (X
IN
–X
OUT
) stop bit (Notes 1, 3)
R
SQ
STP instruction
WIT
instruction
R
S
Q
Reset
Interrupt disable flag I
Interrupt request
R
S
Q
Reset
STP instruction
Timing φ
(Internal clock)
Timer 3
count source selection bit (Notes 1, 2)
“1”
Timer 3 count
stop bit (Notes 1, 2)
Timer 4 count
stop bit (Notes 1, 2)
Timer 3 Timer 4
1/2
1/8
X
OUT
X
IN
“1”
“0”
“0”
Notes 1 : The value at reset is “0.”
2 : Refer to the structure of timer mode register 2.
3 : Refer to the structure of CPU mode register (next page).
4 : Refer to the structure of clock source control register.
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