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Chapter 7. Operation Timing (Memory Expansion and Microprocessor Modes)

7.1 Separate Bus (no wait)

Table 7.1 and Figure 7.1 show bus timing when using the memory expansion mode and micropro-

cessor mode (separate bus, no wait).

Table 7.1 Memory expansion mode and microprocessor mode (separate bus, no wait)

Note 1. Compute bus timing according to BCLK frequency. Use the below formula.

td(DB-WR) = 10

- 40 [ns]

f(BCLK)x2

Note 2. Compute bus timing according to BCLK frequency. Use the below formula.

td(DB-WR) = 10

- 55 [ns]

f(BCLK)x2

Address output delay time

Address output hold time (BCLK)

Address output hold time (RD)

Address output hold time (WR)

Chip-select output delay time

Chip-select output hold time (BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (BCLK)

Data output hold time (BCLK)

Data output delay time (WR)

Data output hold time (WR)

Max.

Symbol

Min.

-4

(Note 1)

Parameter

M306V0EEFP

[ns]

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

M306V0T-RPD-E

[ns]

Min.

-5

-3

-4

(Note 2)

Max.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 49 50

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Renesas M16C/6V Información técnica Pagina 32

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