Renesas R8C/17 Información técnica descargar pdf (Pagina 12)

R8C/16 Group, R8C/17 Group 2. Central Processing Unit (CPU)

Rev.2.00 Jan 30, 2006 Page 10 of 35

REJ03B0101-0200

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and

FB comprise a register bank. Two sets of register banks are provided.

Figure 2.1 CPU Register

b31

b15 b8b7

Data Register

(1)

Address Register

(1)

R0H (high-order of R0)

INTBH

b15b19

INTBL

Frame Bass Register

(1)

The 4-high order bits of INTB are INTBH and

the 16-low bits of INTB are INTBL.

Interrupt Table Register

b19

USP

Program Counter

ISP

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

FLG

Flag Register

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Bit

Processor Interrupt Priority Level

Reserved Bit

IPL

DZSBOIU

b15

NOTES:

1. A register bank comprises these registers. Two sets of register banks are provided.

R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 39 40

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