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3. Trace information cannot be acquired for the following branch instructions:
• The BF and BT instructions whose displacement value is 0
• Branch to H'A0000000 by reset
4. When [User] is specified in the [UBC mode] list box in the [Configuration] window,
the internal trace is not acquired. In this case, exit the [Trace] window.
5. When the SH7619 is used, the source code cannot be displayed on the [Trace]
window.
2.2.3 Note on Using the JTAG Clock (TCK)
Set the JTAG clock (TCK) frequency to lower than the frequency of the SH7619 peripheral
module clock (CKP).
The set value of the JTAG clock (TCK) is initialized by executing [Reset CPU] or [Reset Go].
2.2.4 Notes on Setting the [Breakpoint] Dialog Box
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
Accordingly, it can be set only to the RAM areas in CS0 to CS6 and the internal RAM areas.
However, a BREAKPOINT cannot be set to the following addresses:
• ROM areas in CS0 to CS6
• Areas other than the internal RAM
• Areas other than CS0 to CS6
• A slot instruction of a delayed branch instruction
3. During step operation, BREAKPOINTs are disabled.
4. Conditions set at Break Condition 2 are disabled when an instruction to which a
BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in
which Break Condition 2 is satisfied.
5. When execution resumes from the address where a BREAKPOINT is specified, single-step
operation is performed at the address and execution is continued from the next PC value.
Therefore, realtime operation cannot be performed.
6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
7. When a BREAKPOINT is set to the cacheable area, the cache block containing the
BREAKPOINT address is filled immediately before and after user program execution.
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