Renesas SuperH SH7600 Series Información técnica Pagina 20

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6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
7. When a BREAKPOINT is set to the cacheable area, the cache block containing the
BREAKPOINT address is filled immediately before and after user program execution.
8. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a
mark z will be displayed in the [BP] area of the address on the [Editor] or [Disassembly]
window by refreshing the [Memory] window, etc. after Go execution. However, no break will
occur at this address. When the program halts with the break condition, the mark z disappears.
2.2.6 Notes on Setting the [Break Condition] Dialog Box and BREAKCONDITION_SET
Command
1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Break
Condition 2 are disabled.
2. Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is
executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break
Condition 2.
3. When a Break Condition is satisfied, emulation may stop after two or more instructions have
been executed.
4. If a PC break address condition is set to the slot instruction after a delayed branch instruction,
user program execution cannot be terminated before the slot instruction execution; execution
stops before the branch destination instruction.
5. Note that a break occurs with a break satisfaction condition by an instruction that has been
cancelled due to the generation of an exception.
6. Use the sequential break or count break with the L-bus condition. If such break is used with
the I-bus condition, it will not operate correctly.
7. A break will not occur with the execution counts specified on the execution of the multi-step
instruction.
2.2.7 Notes on Setting the UBC_MODE Command
In the [Configuration] window, if [User] is set while the [UBC mode] list box has been set, the
STEP-type commands that use Break Condition 2 for implementation cannot be used.
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