Renesas PCA4738L-64A Información técnica Pagina 20

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17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3822 Group
MITSUBISHI MICROCOMPUTERS
I/O PORTS
Direction Registers (ports P2, P4
1-P47, and
P5-P7)
The 3822 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0P2, P41P47 and P5-P7). The I/O ports P2,
P41P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
When 0 is written to the bit corresponding to a pin, that pin be-
comes an input pin. When 1 is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When 0 is written to the bit 0 of
a direction register, that port becomes an input port. When 1 is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Fig. 14 Structure of PULL register A and PULL register B
P
00
P
07 pu
ll
-
d
own
P1
0P17 pull-down
P2
0P27 pull-up
P3
4P37 pull-down
P7
0, P71 pull-up
Not used (return 0 when read)
P
U
L
L
r
e
g
i
s
t
e
r
A
(
P
U
L
L
A
:
a
d
d
r
e
s
s
0
0
1
61
6)
b
7
b
0
P
41
P
43 pu
ll
-up
P4
4P47 pull-up
P5
0P53 pull-up
P5
4P57 pull-up
P6
0P63 pull-up
P6
4P67 pull-up
Not used (return 0 when read)
0
:
D
i
s
a
b
l
e
1
:
E
n
a
b
l
e
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
:
a
d
d
r
e
s
s
0
0
1
71
6)
b
7
b
0
N
ote:
Th
e contents o
f
PULL
reg
i
ster
A
an
d
PULL
reg
i
ster
B
do not affect ports programmed as the output port.
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