Renesas PCA7401 Información técnica Pagina 29

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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
26
DATA SLICER
The M37270MF-XXXSP includes the data slicer function for the
closed caption decoder (referred to as the CCD). This function takes
out the caption data superimposed in the vertical blanking interval of
a composite video signal. A composite video signal which makes
the sync chip’s polarity negative is input to the CV
IN pin.
When the data slicer function is not used, the data slicer circuit can
be cut off by setting bit 0 of the data slicer control register 1 (address
00EA
16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB
16)
to “0.” These settings can realize the low-power dissipation.
Fig. 19. Data slicer block diagram
100
0000101
Composite
video
signal
Hundred of kiloohms
to 1 M
Sync pulse counter
register
(address 020F
16
)
Clock run-in register 2
(address 00E7
16
)
Data slicer control register 2
(address 00EB
16
)
Data slicer control register 1
(address 00EA
16
)
Window register
(address 00E2
16
)
Clock run-in register 1
(address 00E6
16
)
Caption position register
(address 00E0
16
)
Start bit position register
(address 00E1
16
)
Clock run-in detect register 1
(address 00E8
16
)
Clock run-in detect register 2
(address 00E9
16
)
Interrupt request
generating circui
t
Data slicer
interrupt
request
Synchronizing
signal counter
Synchronizing
separation
circuit
Sync slice
circuit
Clamping
circuit
Low-pass
filter
Timing signal
generating
circuit
Clock run-in
determination
circuit
Data slice line
specification
circuit
Start bit detecting
circuit
Data clock
generating circui
t
16-bit shift register
Data register 1
(address 00E4
16
)
Data register 2
(address 00E5
16
)
Sync slice
register 3
(address
00E3
16
)
Data bus
Comparator
010111
000
000
00
0101
0.1 F
470
560 pF
CV
IN
1 F
1 k
200 pF
15 k
H
SYNC
HLF RVCO
+
Reference
voltage
generating
circuit
V
HOLD
1000 pF
high-order low -
order
Data slicer ON/OFF
Data register 4
(address 00ED
16
)
Data register 3
(address 00EC
16
)
Data slicer control
register 3
(address 0210
16
)
Clock run-in detect
register 3
(address 0208
16
)
Clock run-in
register 3
(address 0209
16
)
External circui
t
Note : Make the length of wiring which
is connected to V
HOLD
, HLF,
RVCO and CV
IN
pin as short as
possible so that a leakage
current may not be generated
when mounting a resistor or a
capacitor on each pin.
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