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MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

000

Data slicer control register 1

(DSC1: address 00EA

16)

Data slicer control bit

0: Data slicer stopped

1: Data slicer operating

Field to be sliced data selection bit

Fix this bit to “0.”

Data latch completion flag for caption

data in main data slice line

0: Data is not yet latched

1: Data is latched

Field determination flag

000

sep

0 :

1 :

Field of main data

slice line

Field for setting

reference voltage

b2 b1

0 0 F2

0 1 F1

1 0 and F2

1 1 and F2

Definition of fields 1 (F1) and 2 (F2)

sep

SYNC

sep

F1 :

sep

SYNC

sep

F2 :

Data slicer control register 3

(DSC3: address 0210

16)

Line selection bit for slice voltage

0: Main data slice line

1: Sub-data slice line

Field of sub-data

slice line

b2 b1

0 0 F2

0 1 F1

1 0 F1 and F2

1 1 F1 and F2

Field to be sliced data selection bit

Setting bit of sub-data slice line

Field for setting

reference voltage

Fix these bits to “0.”

Data slicer control register 2

(DSC2: address 00EB16)

Timing signal generating circuit

control bit

0: Stopped

1: Operating

Reference clock source selection

bit

0: Video signal

1: HSYNC signal

Test bit: read-only

Fix these bits to “0.”

V-pulse shape determination flag 

0: Match

1: Mismatch

Fix this bit to “0.”

Test bit: read-only

Figure 19 shows the structure of the data slicer control registers.

Fig. 20. Structure of data slicer control registers

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 96 97

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