Renesas Single-Chip Microcomputer SH7203 Información técnica descargar pdf (Pagina 17)

Reference Function ON OFF

SW4-4 USB

VBUS (pin 102) of the CPU monitors

Host VBUS.

HOST_VBUS_FLAG is disconnected

from VBUS (pin 102) of the CPU.

SW4-5 USB VBUS (pin 102) of the CPU monitors

Device VBUS.

DEVICE_VBUS is disconnected from

VBUS (Pin 102) of the CPU.

Please note that only one switch can be set to ON.

Table 6-14 VBUS connection

Reference Function ON OFF

SW4-6 SSI PF30 (Pin 128) of the CPU can be

used as AUDIOCLK signal on J2.

AUDIOCLK signal on J2 is

disconnected from Pin 128 of the CPU.

SW4-7 RCAN

PF30 (Pin 128) of the CPU can be

used as CAN1_EN.

Pin 128 of the CPU can not be used as

CAN1_EN signal.

Please note that only one switch can be set to ON.

Table 6-15 PF30 function select

Reference Function ON OFF

SW4-8 CLOCK

Mode

The MD_CLK0 (Pin 97) of the CPU

logic 0

The MD_CLK0 (Pin 97) of the CPU

logic 1

SW4-9 CLOCK

Mode

The MD_CLK1 (Pin 96) of the CPU

logic 0

The MD_CLK1 (Pin 96) of the CPU

logic 1

Table 6-16 Clock mode settings

Reference Function ON OFF

SW4-10 BUS Interface 16 bit bus interface is selected for

SDRAM access. Port functions on

upper 16 bits.

32 bit bus interface is selected

for SDRAM access.

Table 6-17 32 bit/16 bit select

Reference Function ON OFF

SW5-1 LCD / NAND

FLASH

Pin 147 of the CPU is connected to

NAND_CSn pin of NAND Flash.

NAND flash disabled

Table 6-18 NAND Flash enable

Reference Function ON OFF

SW5-2 External ROM Disables writing to the External Flash

memory.

Enables writing to the External Flash

memory.

Table 6-19 Flash protection

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 32 33

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