Renesas Asynchronous SH7145F Manual de usuario descargar pdf (Pagina 5)

SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 5 of 20

2.2 Compare-Match Timer (CMT)

The CMT generates an interrupt at given intervals. Figure 3 is a block diagram of the CMT module channel 0 (ch0);

below, functions are explained referring to figure 3.

Interrupt

request:

CMI0

Clock selection

Comparator

Clock

Control circuit

Compare-match

timer start register

(CMSTR)

Compare-match

timer counter_0

(CMCNT_0)

Compare-match

timer constant register_0

(CMCOR_0)

Compare-match timer control/

status register_0

(CMTCSR_0)

Internal

peripheral

clocks:

Pφ/8

Pφ/32

Pφ/128

Pφ/512

< CMT0 function block >

Figure 3 CMT (ch0) Block Diagram

• The CMT has a 16-bit counter, and can generate an interrupt at given intervals.

• A clock signal obtained by dividing the internal peripheral clock Pφ can be selected. The counter is incremeted by

the selected clock.

• The compare-match timer start register (CMSTR) starts or stops counting.

• The compare-match timer control/status register (CMCSR_0) indicates compare-match occurrence, sets up

interrupts, and selects the count-up clock.

• The compare-match timer counter (CMCNT_0) is an up-counter used to generate interrupt requests.

• The compare-match timer constant register (CMCOR_0) sets the compare-match interval.

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Renesas Asynchronous SH7145F Manual de usuario Pagina 5