Renesas Asynchronous SH7145F Manual de usuario descargar pdf (Pagina 6)

SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 6 of 20

3. Description of Operation

Figure 4 shows the operation during reception in asynchronous mode in this sample task. As an explanation of figure 4,

table 3 describes the software and hardware processing.

RxD0 (pin)

CMCNT_0

H'0F42

5 msec

Start

bit

Start

bit

Data

Third data item

Stop

bit

5 msec 5 msec

Time

(7)

(8)(6)

(4)

(5)

(1)

(2)

(3)

Figure 4 Operation during Data Reception

Table 3 Description of Processing

Software Processing Hardware Processing

(1) Framing error processing Set the FER bit in SSR_0 to 1.

(2) Set the STR0 bit in CMSTR to 1. Start counting by CMT0.

(3) 

Set the CMF flag (generate a compare-match

interrupt).

(4) Clear the CMF flag to 0. Start counting by CMT0.

(5) Read RxD pin level. 

(6) Repeat steps (3) through (5) twice. Repeat steps (3) through (5) twice.

(7) Clear the STR0 bit in CMSTR to 0. Stop operation of CMT0.

(8) Clear the RE bit in SCR0 to 0. Stop reception by SCI0.

1 2 3 4 5 6 7 8 9 10 11 ... 19 20

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Renesas Asynchronous SH7145F Manual de usuario Pagina 6