Renesas Asynchronous SH7145F Manual de usuario descargar pdf (Pagina 9)

SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 9 of 20

Table 7 Description of Internal Registers (3)

Name Bit Bit Name Setting Function

Module standby control register 2

MSTCR2

12 MSTP12 0 CMT standby control bit

When MSTP12 = 0, cancels the standby state of the

CMT.

H'01 Compare-match timer start register

15 to 2  0 Reserved

1 STR1 0 Count start 1

When STR1 = 0, the CMCNT_1 stops counting.

CMSTR

0 STR0 1 Count start 0

When STR0 = 1, the CMCNT_0 starts counting.

Compare-match timer control/status register_0

15 to 8  0 Reserved

7 CMF * Compare-match flag

When CMF=1, CMCNT and CMCOR values match.

6 CMIE 1 Compare-match interrupt enable

Enables or disables compare-match interrupts. When

CMIE=1, compare-match interrupts are enabled.

5 to 2  0 Reserved

CMCSR_0

CKS1

CKS0

CMCNT_0 input clock select 1, 0

In this sample task, Pφ/32 is selected.

CMCNT_0  Compare-match timer counter_0

Up-counter used to generate interrupt requests.

CMCOR_0 H'0F42 Compare-match timer constant register_0

Specify the interval of compare-match with CMCNT_0.

H'00F0 Interrupt priority register G

Sets priority levels for interrupt sources.

IPRG

7 to 4 IPR7

IPR6

IPR5

IPR4

These bits set the priority level of CMT0 (0-15).

Note: * Only clearing is possible; setting to 1 is done by hardware.

4.3 Description of Arguments

Arguments used in this sample task are described in table 8.

Table 8 Description of Arguments

Argument Name Function Used in

Rev_data[0 to 2] Stores data received by SCI0 Receive routine

T_count

Counts the number of CMT0

interrupts

CMT0 interrupt routine, error processing routine

Rd_count

Number of times level is low when

RxD pin level is read

CMT0 interrupt routine, error processing routine

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 19 20

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