Renesas M16C FAMILY Manual de usuario descargar pdf (Pagina 17)

■ Intelligent I/O

I/O ports can be configured to implement different peripheral functions.

ICC

The following waveform output modes are implemented on all groups.

(1) Single-Phase Waveform Output (2) Inverted Waveform Output

(3) SR Waveform Output

Digital Filter Function (INPC10 to INPC17)

Output Compare (Waveform Generator Function)

Interrupts are generated when matches occur between the base timer

and waveform generator register values, generating a PWM waveform.

Bit Modulation PWM

High-frequency PWM output can be produced based on any bit

between 6 and 16.

Input Capture (Time Measurement Function)

At trigger input, the timer value is stored in the time measurement

Input Capture (Digital Filter Function)

The trigger input level is determined every f

or f

BT1,

and pulses are

allowed to pass through when three matches occur. (The clock of

the digital filter can be selected to match the noise band.)

OFFFF

Base Timer Value

Waveform Generator

OUTCx1

Single-Phase Waveform Output OUTCx0

Inverted Waveform Output OUTCx0

SR Waveform Output OUTCx0

Interrupt Request at Match with

Waveform Generator Register 0 Value

Interrupt Request at Match with

Waveform Generator Register 1 Value

Elapsed Time

k=0~3F16 m=0~3FF16

Waveform Generator

PWM Duty Setting Bit Modulation Rate of Recurrence

Base Timer Count

Source

Output Waveform

PWM Frequency (4016)

PWM Duty (k)

Among 1,024 pulses,

m pulses are added

to the clock cycle duty.

D/A Converter Application Example Using PWM Output

High-resolution output can be

obtained by changing the PWM

duty by one clock cycle at a

user-defined rate of recurrence.

Trigger Input to

INPC Pin

Base Timer

Count Source

Base Timer

Value

Time Measurement

(Both Edges Selected)

Time Measurement

Interrupt Request

Cleared to 0

by a program.

Filter Clock

1 or fBT1)

INPC Pin

Trigger Signal After

Passing Through

Digital Filter

Signal Delay Caused by Digital Filter

(Max. 3.5 Cycles of Filter Clock)

Signals that do not match three times are eliminated.

1111111111

32 16 8 4 2 1

2 4 8 16 32 64 128 256 512 1024

0b9b01b51b

■ On-board LCD Controller Circuit

Example: Three 7-segment Digits

(6 SEG; 4 COM)

FGED ABC FGED ABC FGED ABC

• Segment- or Dot Matrix-type support

• Up to 56 Segment lines and

8 Common lines for a maximum

of 416 LCD segments/dots

• Internal multiplier function for

LCD voltage supply

• Supports 3V or 5V LCD glass

• 1/2, 1/3 and 1/4 Bias options

(internal or external configuration)

• Automatic Blink Function for

each segment independently

• Multiple clock sources

including 32kHz Sub-clock

• Dedicated LCD RAM area for display and control

of each segment

• All SEG and COM pins are multiplexed with GPIO

LCD Clock Circuit

LCD

Display

Data

Registers

COMMON

Lines Circuit

SEGMENT

Lines Circuit

LCD DRIVE

VOLTAGE

Circuit

Control

Registers

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 45 46

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Renesas M16C FAMILY Manual de usuario Pagina 17

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