Renesas M16C FAMILY Manual de usuario descargar pdf (Pagina 30)

R8C/2x, 3x Series



Optimized pin assignment compatibility between 20- to 80-pin

devices in R8C/3x series



No connection-crossing makes scaling (up or down) quick and simple



Numerous SSOPs, QFPs, and QFN packages with different dimensions

allows easy layout of multiple package footprints on one circuit board



Package details (arranged by body size):

24-pin QFN: 4mm x 4mm, 0.5mm pitch

20-pin LSSOP: 4.4mm x 6.5mm, 0.65mm pitch

32-pin LQFP: 7mm x 7mm, 0.8mm pitch

48-pin LQFP: 7mm x 7mm, 0.5mm pitch

52-pin LQFP: 10mm x 10mm, 0.65mm pitch

80-pin LQFP: 12mm x 12mm, 0.5mm pitch

64-pin LQFP: 14mm x 14mm, 0.8mm pitch

Example:

20-pin LSSOP inside 32-pin LFQP

SYSTEM PINS

Optimized Pin Compatibility

On-chip Debug Unit

R8C/2x R8C/3x

Hardware & Monitor Enhanced Hardware

Communication

speciﬁ cation

Serial

Interface

Asynchronous Asynchronous

Base clock

Internal

on-chip oscillator

Internal

on-chip oscillator

Break

Before

execution

Address match:

up to 2 points

Address match:

8 points

Trace

information

Branch destination:

4 points

Branch/data access:

8 points

Trace

condition

Not available

Combination of

2 points

Memory Modiﬁ cation

during execution

By monitor program By Debug DMA



Unified Interface

• Debugging and Programming



Physical Connection

• 1 wire (dedicated MODE pin)



Break Points (Type)

• Address and Data

VCC

AVCC

RESET

GND

Reset

signal

MODE

E8 or E8a

Emulator

1-Wire On-chip Debugging & Programming

RAM

Control file (for ch. 1)

Control file (for ch. 2)

Control file (for ch. 3)

Control file (for ch. n)

Control registers

DTC



Load

Control file

to Control



Write back

Control file

after

transferring



Trigger

Data buffer



Read data

from source



Write data to destination

 Interrupt (for ch. 3) from peripheral

SFR/

RAM/ROM

source

SFR/

RAM

destination

R8C/3x devices incorporate a

DMA-like engine which allows data

transfers between memory and

peripherals without CPU intervention,

increasing overall performance

significantly. Data can be transferred

automatically within the first 64KB of

memory. The DTC is activated by

software control or by a peripheral

interrupt providing fast response.

transfer is defined in a ‘Control File’

(i.e., channel) which is located

in RAM. A maximum of 24 channels

can be set up in the MCU. Each

transfer can be made up of up to 256

bytes and can occur up to 256 times

in normal or repeat mode.

Data Transfer Controller

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 45 46

Comentarios a estos manuales

Sin comentarios

Renesas M16C FAMILY Manual de usuario Pagina 30

Comentarios a estos manuales

Relacionado con productos y manuales para Redes Renesas M16C FAMILY