Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 10)

SH7080 Group

A/D Conversion in Single-cycle Scan Mode

REJ06B0699-0100/Rev.1.00 January 2008 Page 8 of 19

A more detailed view of the timing is given in figure 4. Processing at the numbered points is described in table 3.

Firstly, the mode, channel, clock, etc., are selected with ADCSR_0 and ADCR_0 ((1) in figure 4).

Then, the ADST bit in ADCR_0 is set to 1 to start A/D conversion (figure 4, (2) and (3)). At the end of each round of

A/D conversion on all the channels (0 to 3), the converted data are stored in bits 15 to 6 of the corresponding register

from ADDR0 to ADDR3 (figure 4, (4)). The ADF bit is set to 1 after conversion on all channels has been completed

(figure 4, (5)). Also, the ADST bit is cleared to 0 (figure 4, (6)). In single-cycle scan mode, A/D conversion is

performed only once on each specified channel (in this sample application, A/D conversion is performed once on each

of the channels AN0 to AN3). After that, the ADF flag of ADCSR_0 is cleared to 0 (figure 4, (7)) and data from all the

four registers are stored in the on-chip RAM (figure 4, (8)).

Steps (2) to (8) shown in figure 3 are repeated twice (figure 4, (9) and (10)).

ADF

ADST

ADDR0

ADDR1

ADDR2

ADDR3

(1) (4) (5)

(6)

(7) (8) (9) (10)(2)

(3)

A/D

converter

Standby StandbyA/D conversion

A/D-

converted

data (AN1)

A/D-

converted

data (AN2)

A/D-

converted

data (AN3)

A/D-

converted

data (AN0)

A/D-

converted

data (AN1)

A/D-

converted

data (AN2)

A/D-

converted

data (AN3)

A/D-

converted

data (AN0)

On-chip RAM

Second round of A/D conversion

Third round of A/D conversion

Figure 4 Details on the Timing of A/D Conversion

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 20 21

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