Renesas SH7709S Manual de usuario descargar pdf (Pagina 13)

Rev. 1.0, 07/03, page 9 of 38

Vdd

VddQ

Vss

VssQ

3.3V

GND

Vdd

VddQ

Vss

VssQ

3.3V

GND

A15

SH7709S/SH7729R/SH7706 64-Mbit SDRAM(×16)

64-Mbit SDRAM(×16)

A14

A13

CKIO

CKE

( )

RD/

DQMUU

DQMUL

D31

D16

D15

BA1

BA0

A11

CLK

CKE

DQMU

DQML

DQ15

DQ0

BA1

BA0

A11

CLK

CKE

DQMU

DQML

DQ15

DQ0

DQMLU

DQMLL

Figure 2.2 Interface between SDRAM (HM5264165TT-B60) and

SH7709S/SH7729R/SH7706

2.1.5 uPD45128163 (2 Mwords × 16 bits × 4 banks)

Bus State Controller (BSC) Settings: When two SDRAMs (uPD45128163) are connected to area

3 of the SH7709S/SH7729R/SH7706 via a 16-bit bus, the bus state controller (BSC) must be

specified as summarized below. Table 2.3 lists the BSC register settings. Note that the interface

between the SDRAM and the SH7709S/SH7729R/SH7706 is performed with bus clock = 66

MHz, CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 3.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 43 44

SH-3, SH3-DSP SDRAM Interface 1
Cautions 2
Rev. 1.0, 07/03, page 3
Contents 4
Rev. 1.0, 07/03, page 2 of 38 6
Rev. 1.0, 07/03, page 3 of 38 7
Rev. 1.0, 07/03, page 4 of 38 8
Rev. 1.0, 07/03, page 5 of 38 9
Register Name 10
Rev. 1.0, 07/03, page 7 of 38 11
Rev. 1.0, 07/03, page 9 of 38 13

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