
Rev. 1.0, 07/03, page 23 of 38
By writing data to address H'FFFFD000 + X or address H'FFFFE000 + X, the precharge all banks
command (PALL) is first issued at cycle TRp1, and a mode register write command is issued at
the following cycle TMw1. The address signals when a mode register write command is issued are
as follows.
32-bit bus width A15 to A9 0000100 (Burst read and single write)
A8 to A6 CAS latency
A5 0 (Burst type = sequential)
A4 to A2 000 (Burst length 1)
16-bit bus width A14 to A8 0000100 (Burst read and single write)
A7 to A5 CAS latency
A4 0 (Burst type = sequential)
A3 to A1 000 (Burst length 1)
Before specifying the mode register, 100 µs of idle time (differs depending on the memory
manufacturer) required for synchronous DRAM must be ensured after power-on. If the pulse
width of the reset signal is longer than this idle time, the mode register can be specified
immediately after power-on. In addition, dummy auto-refresh cycles must be executed for the
number of times specified by the manufacturer (normally 8 times) or more. Dummy auto-refresh
cycles are normally specified to be executed automatically during initializations after auto-refresh
setting. However, to ensure execution of the auto-refresh cycles, the time intervals between refresh
requests must be shortened while the dummy cycles are executed. Note that the auto-refresh cycles
must be executed in order to initialize the synchronous DRAM internal address counter because
the synchronous DRAM internal address counter cannot be initialized by a normal read or write
access.
2.2.3 HM5264165F-B60 (1 Mword × 16 bits × 4 banks)
Bus State Controller (BSC) Settings: When an SDRAM (HM5264165F-B60) is connected to
area 3 of the SH7727 via a 16-bit bus, the bus state controller (BSC) must be specified as
summarized below. Table 2.8 lists the BSC register settings.
Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,
CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.
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