Renesas SH7709S Manual de usuario descargar pdf (Pagina 34)

Rev. 1.0, 07/03, page 30 of 38

Vdd

VddQ

Vss

VssQ

3.3V

GND

A14

SH7727 128-Mbit SDRAM(×16)

A13

A12

CKIO

CKE

RD/

DQMLU

DQMLL

D15

BA1

BA0

A11

CLK

CKE

DQMU

DQML

DQ15

DQ0

Figure 2.10 Interface between SDRAM (uPD45128163) and SH7727

2.2.6 uPD45128163 (2 Mwords × 16 bits × 4 banks)

Bus State Controller (BSC) Settings: When two SDRAMs (uPD45128163) are connected to area

3 of the SH7727 via a 32-bit bus, the bus state controller (BSC) must be specified as summarized

below. Table 2.11 lists the BSC register settings.

Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,

CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 43 44

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Renesas SH7709S Manual de usuario Pagina 34