Renesas SH7709S Manual de usuario

32Rev. 1.002003.7.31www.renesas.comRenesas 32-bit RISC MicrocomputerSuperHTM RISC engine Family/SH7000 SeriesSH-3, SH3-DSP SDRAM InterfaceSH7709S/SH77

Rev. 1.0, 07/03, page 6 of 38Table 2.1 BSC Register Settings (HM5264165F-B60)Register NameAbbr. InitialValueAddressAccessSizeSetting ValueBus control

Rev. 1.0, 07/03, page 7 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA14SH7709S/SH7729R/SH7706 64-Mbit SDRAM(×16)64-Mbit SDRAM(×16)A13A12::::A1CKIOC

Rev. 1.0, 07/03, page 8 of 38Table 2.2 BSC Register Settings (HM5264165TT-B60)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page 9 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA15SH7709S/SH7729R/SH7706 64-Mbit SDRAM(×16)64-Mbit SDRAM(×16)A14A13::::A2CKIOC

Rev. 1.0, 07/03, page 10 of 38Table 2.3 BSC Register Settings (uPD45128163)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control r

Rev. 1.0, 07/03, page 11 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA14SH7709S/SH7729R/SH7706 128-Mbit SDRAM(×16)128-Mbit SDRAM(×16)A13A12::::A1CK

Rev. 1.0, 07/03, page 12 of 38Table 2.4 BSC Register Settings (uPD45128163)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control r

Rev. 1.0, 07/03, page 13 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA15SH7709S/SH7729R/SH7706 128-Mbit SDRAM(×16)128-Mbit SDRAM(×16)A14A13::::A2CK

Rev. 1.0, 07/03, page 14 of 382.1.7 HM5225165B-B6 (4 Mwords × 16 bits × 4 banks)Bus State Controller (BSC) Settings: When two SDRAMs (HM5225165B-B6) a

Rev. 1.0, 07/03, page 15 of 38Table 2.5 BSC Register Settings (HM5225165B-B6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control

CautionsKeep safety first in your circuit designs!1. Renesas Technology Corporation puts the maximum effort into making semiconductorproducts better a

Rev. 1.0, 07/03, page 16 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA15SH7709S/SH7729R/SH7706 64-Mbit SDRAM(×16)64-Mbit SDRAM(×16)A14A13::::A1CKIO

Rev. 1.0, 07/03, page 17 of 38Table 2.6 BSC Register Settings (HM5225165B-B6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control

Rev. 1.0, 07/03, page 18 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA16SH7709S/SH7729R/SH7706 256-Mbit SDRAM(×16)256-Mbit SDRAM(×16)A15A14::::A2CK

Rev. 1.0, 07/03, page 19 of 382.1.9 HM5257165B-A6 (8 Mwords × 16 bits × 4 banks)Bus State Controller (BSC) Settings: When an SDRAM (HM5257165B-A6) is

Rev. 1.0, 07/03, page 20 of 38Table 2.7 BSC Register Settings (HM5257165B-A6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control

Rev. 1.0, 07/03, page 21 of 38VddVddQVssVssQ3.3VGNDA15SH7709S/SH7729R/SH7706 512-Mbit SDRAM(×16)A14A13::::::::A1CKIOCKE( )RD/DQMLUDQMLLD15D0BA1BA0A12:

Rev. 1.0, 07/03, page 22 of 38The RAS3, CAS and RD/WR signals and specific address signals specify a command forsynchronous DRAM. The synchronous DRAM

Rev. 1.0, 07/03, page 23 of 38By writing data to address H'FFFFD000 + X or address H'FFFFE000 + X, the precharge all bankscommand (PALL) is

Rev. 1.0, 07/03, page 24 of 38Table 2.8 BSC Register Settings (HM5264165F-B60)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page 25 of 38VddVddQVssVssQ3.3VGNDA14SH7727 64-Mbit SDRAM(×16)A13A12::::A1CKIOCKERD/DQMLUDQMLLD15D0BA1BA0A11::::A0CLKCKEDQMUDQMLDQ15D

Rev. 1.0, 07/03, page i of iiPrefaceThe SuperHTM RISC engine microcomputer is new generation RISC microcomputer that provideshigh-performance operatio

Rev. 1.0, 07/03, page 26 of 38 2.2.4 HM5264165F-B60 (1 Mword × 16 bits × 4 banks)Bus State Controller (BSC) Settings: When two SDRAMs (HM5264165F-B60)

Rev. 1.0, 07/03, page 27 of 38Table 2.9 BSC Register Settings (HM5264165F-B60)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page 28 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA15SH7727 64-Mbit SDRAM(×16)64-Mbit SDRAM(×16)A14A13::::A2CKIOCKERD/DQMUUDQMUL

Rev. 1.0, 07/03, page 29 of 38Table 2.10 BSC Register Settings (uPD45128163)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control

Rev. 1.0, 07/03, page 30 of 38VddVddQVssVssQ3.3VGNDA14SH7727 128-Mbit SDRAM(×16)A13A12::::A1CKIOCKERD/DQMLUDQMLLD15D0BA1BA0A11::::A0CLKCKEDQMUDQMLDQ15

Rev. 1.0, 07/03, page 31 of 38Table 2.11 BSC Register Settings (uPD45128163)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus control

Rev. 1.0, 07/03, page 32 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA15SH7727 128-Mbit SDRAM(×16)128-Mbit SDRAM(×16)A14A13::::A2CKIOCKERD/DQMUUDQM

Rev. 1.0, 07/03, page 33 of 38Table 2.12 BSC Register Settings (HM5225165B-B6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page 34 of 38VddVddQVssVssQ3.3VGNDA15SH7727 256-Mbit SDRAM(×16)A14A13::::A1CKIOCKERD/DQMLUDQMLLD15D0BA1BA0A12::::A0CLKCKEDQMUDQMLDQ15

Rev. 1.0, 07/03, page 35 of 38Table 2.13 BSC Register Settings (HM5225165B-B6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page ii of iiContentsSection 1 How to Use the Application Notes1.1 Configuration of SDRAM Interface Examples...

Rev. 1.0, 07/03, page 36 of 38VddVddQVssVssQ3.3VGNDVddVddQVssVssQ3.3VGNDA16SH7727 256-Mbit SDRAM(×16)256-Mbit SDRAM(×16)A15A14::::A2CKIOCKERD/DQMUUDQM

Rev. 1.0, 07/03, page 37 of 38Table 2.14 BSC Register Settings (HM5257165B-A6)Register Name Abbr. InitialValueAddressAccessSizeSetting ValueBus contro

Rev. 1.0, 07/03, page 38 of 38VddVddQVssVssQ3.3VGNDA15SH7727 512-Mbit SDRAM(×16)A14A13::::::::A1CKIOCKERD/DQMLUDQMLLD15D0BA1BA0A12::::::::A0CLKCKEUDQM

SH-3, SH3-DSP SDRAM Interface Application Note(SH7709S/SH7729R/SH7706/SH7727)Publication Date: 1st Edition, July 31, 2003Published by: Sales Stra

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, JapanSH-3, SH3-DSP SDRAM InterfaceREJ05B0077-0100H

Rev. 1.0, 07/03, page 1 of 38Section 1 How to Use the Application Notes1.1 Configuration of SDRAM Interface ExamplesThe SDRAM interface examples in

Rev. 1.0, 07/03, page 2 of 38

Rev. 1.0, 07/03, page 3 of 38Section 2 SDRAM Interface Examples2.1 SH7709S/SH7729R/SH7706 to SDRAM Interface Examples2.1.1 SDRAM Direct ConnectionSyn

Rev. 1.0, 07/03, page 4 of 38Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write isperformed for the byte for which the co

Rev. 1.0, 07/03, page 5 of 38A7 to A5 CAS latencyA4 0 (Burst type = sequential)A3 to A1 000 (Burst length 1)Before specifying the mode register, 100 µ