Renesas PROM Programming Adapter PCA7435FPG02 Manual de usuario descargar pdf (Pagina 19)

7540 Group

Rev.4.00 Jun 21, 2004 page 19 of 82

REJ03B0011-0400Z

Fig. 18 Block diagram of ports (2)

Pull-up control

INT interrupt input

P3 input level

selection bit

(11) Ports P3

–P3

Pull-up control

(9) Port P1

Data bus

Serial I/O1 ready output

Serial I/O2 output

Serial I/O2 input

DATA2

pin selection bit

Port latch

Direction

DATA2

output in operation signal

CNTR

interrupt input

Pulse output mode

Timer output

, P1

input level

selection bit

Serial I/O mode selection bit

Serial I/O1 enable bit

RDY1

output enable bit

, P1

, P3

, and P3

input level are switched to the CMOS/TTL level by the port P1P3 control register.

Data bus

Port

latch

Direction

Data bus

Port

latch

Direction

Data bus

Port latch

Direction

A/D converter input

Analog input pin

selection bit

(12) Ports P3

, P3

Data bus

Port

latch

Direction

(10) Ports P2

–P2

(8) Port P1

When the TTL level is selected

there is no h

steresis characteristics.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 87 88

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