
7540 Group
Rev.4.00 Jun 21, 2004 page 32 of 82
REJ03B0011-0400Z
Fig. 28 Block diagram of timer 1 and timer A
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Data bus
P0
0
/CNTR
1
CNTR
1
active
edge switch bit
f(X
IN
)/16
Rising edge detected
Falling edge detected
Timer A operation mode bit
Timer A count
stop bit
Prescaler 1 latch (8)
Prescaler 1 (8)
Timer 1 latch (8)
Timer 1 (8)
f(X
IN
)/16
Data bus
Timer A interrupt
request bit
Timer 1 interrupt
request bit
Pulse width HL
continuously
measurement mode
Period measurement mode
Comentarios a estos manuales