Renesas PROM Programming Adapter PCA7435FPG02 Manual de usuario descargar pdf (Pagina 5)

7540 Group

Rev.4.00 Jun 21, 2004 page 5 of 82

REJ03B0011-0400Z

Fig. 6 Functional block diagram (36P2R package)

FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)

A/D

converter

(10)

X

IN OUT

X

CPU

V

SS

18

RESET

13

V

CC

15

14

CNV

SS

P0(8)

34

32 30

28

33

31

29 27

P1(5)

31

35

2

36

7

56

4

P2(8)

P3(8)

2023 21 19

12

I/O port P2

I/O port P0

I/O port P1

I/O port P3

16 17

11

9

10

8

0

22

26 2425

SI/O1(8)

RAM

ROM

A

X

Y

S

PC

H

PC

L

PS

Reset input

Clock generating circuit

Clock input

Clock output

V

REF

Watchdog timer

Reset

INT

0

SI/O2(8)

CNTR

0

Prescaler Y (8)

Prescaler Z (8)

Timer X (8)

Timer Z (8)

Timer Y (8)

Key-on wakeup

TY

OUT

TZ

OUT

Prescaler X (8)

CNTR

1

Timer A (16)

INT

0

Timer 1 (8)

Prescaler 1 (8)

TX

OUT

INT

1

1 2 3 4 5 6 7 8 9 10 ... 87 88

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