Renesas PROM Programming Adapter PCA7435FPG02 Manual de usuario descargar pdf (Pagina 35)

7540 Group

Rev.4.00 Jun 21, 2004 page 35 of 82

REJ03B0011-0400Z

Fig. 32 Block diagram of UART serial I/O1

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O1 mode selection bit of the serial I/O1 control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

XIN

1/4

PE FE

1/16

Data bus

Receive buffer register

Address 001816

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C

ST/SP/PA generator

Transmit buffer register

Data bus

Transmit shift register

Address

0018

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address

0019

ST detector

SP detector

UART control register

Address 001B

Character length selection bit

Address 001A

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O1 synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O1 control register

2/SCLK1

Serial I/O1 status register

0/RXD1

P11/TXD1

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 33 Operation of UART serial I/O1 function

TSC=0

TBE=1

RBF=0

TBE=0 TBE=0

RBF=1

STD0 D1 SP D0 D1

TBE=1

TSC=1

STD0 D1

D0 D1

ST SP

Transmit or receive clock

Transmit buffer write

signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O1 control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1.”

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

✽

Serial output TXD

Serial input R

Receive buffer read

signal

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 87 88

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