Renesas 4513 Información técnica descargar pdf (Pagina 44)

4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Table 16 Change of successive comparison register AD during A-D conversion

Comparison voltage (Vref) value

Change of successive comparison register ADAt starting conversion

(7) Operation description

A-D conversion is started with the A-D conversion start instruction

(ADST). The internal operation during A-D conversion is as follows:

➀ When A-D conversion starts, the register AD is cleared to

“000

16.”

➁ Next, the topmost bit of the register AD is set to “1,” and the

comparison voltage V

ref is compared with the analog input volt-

age VIN.

➂ When the comparison result is Vref < VIN, the topmost bit of the

Vref > VIN, it is cleared to “0.”

The 4513/4514 Group repeats this operation to the lowermost bit of

the register AD to convert an analog value to a digital value. A-D

conversion stops after 62 machine cycles (46.5

s when f(XIN) =

4.0 MHz in high-speed mode) from the start, and the conversion re-

sult is stored in the register AD. An A-D interrupt activated condition

is satisfied and the ADF flag is set to “1” as soon as A-D conversion

completes (Figure 27).

✼1: 1st comparison result

✼3: 3rd comparison result

✼9: 9th comparison result

✼2: 2nd comparison result

✼8: 8th comparison result

✼A: 10th comparison result

1st comparison

2nd comparison

3rd comparison

After 10th comparison

completes

✼1

-----

✼2

✼3

✼8

✼9

✼A

A-D conversion result

VDD

1024

-------------

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 98 99

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