Renesas 4513 Información técnica descargar pdf (Pagina 58)

4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

CLOCK CONTROL

The clock control circuit consists of the following circuits.

• System clock generating circuit

• Control circuit to stop the clock oscillation

Fig. 41 Clock control circuit structure

Table 23 Clock control register MR

Note : “R” represents read enabled, and “W” represents write enabled.

• Control circuit to switch the middle-speed mode and high-speed

mode

• Control circuit to return from the RAM back-up state

MR3

MR2

MR1

MR0

Clock control register MR

f(XIN) (high-speed mode)

f(XIN)/2 (middle-speed mode)

This bit has no function, but read/write is enabled.

System clock selection bit

Not used

at reset : 10002 at RAM back-up : 10002

R/W

Instruction clock

RESET

Falling detected

Ports P0

, P0

Ports P0

, P0

Ports P1

, P1

Ports P1

, P1

Multi-

plexer

,K0

Counter

Wait time (Note)

control circuit

Software

start signal

POF instruction

OUT

“L” level

/INT

Key-on wake up control register

/INT

Oscillation

circuit

Division circuit

(divided by 2)

Internal clock

generation circuit

(divided by 3)

“H” level

“L” level

“H” level

Note: The wait time control circuit is used to generate the time required to stabilize the f(X

) oscillation.

System clock

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 98 99

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Renesas 4513 Información técnica Pagina 58

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