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R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode

Rev.1.20 Jan 27, 2006 page 100 of 180

REJ09B0019-0120

Table 13.5 Registers to Be Used and Settings in UART Mode

UiTB 0 to 8 Set transmission data

(1)

UiRB 0 to 8 Reception data can be read

(1)

OER,FER,PER,SUM

Error flag

UiBRG 0 to 7 Set a bit rate

UiMR SMD2 to SMD0 Set these bits to ‘100

2’ when transfer data is 7 bits long

Set these bits to ‘1012’ when transfer data is 8 bits long

Set these bits to ‘1102’ when transfer data is 9 bits long

CKDIR Select the internal clock or external clock

(2)

STPS Select the stop bit

PRY, PRYE Select whether parity is included and whether odd or even

UiC0 CLK0, CLK1 Select the count source for the UiBRG register

TXEPT Transmit register empty flag

NCH Select TxDi pin output mode

CKPOL Set to “0”

UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this

bit to “0” when transfer data is 7 or 9 bits long.

UiC1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt

U0RRM Set to “0”

TXD1SEL Select output pin for UART1 transfer data

TXD1EN Select TxD10 or RxD1 to be used

NOTES:

1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0

to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.

2. An external clock can be selected in UART0 only.

Table 13.6 lists the functions of the input/output pins during UART mode. Note that for a period from when

the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the NCH bit

is set to “1”(N-channel open-drain output), this pin is in high-impedance state.)

Table 13.6 I/O Pin Functions in UART Mode

Pin name Function Method of selection

TxD

(P1

)

Serial data output

Serial data input

Programmable I/O port

Transfer clock input

Serial data output

(Cannot be used as a port when performing reception only)

RxD

(P1

)

CLK

(P1

) U0MR register CKDIR bit=0

U0MR register CKDIR bit=1

PD1 register PD1_6 bit=0

PD1 register PD1_5 bit=0

(Can be used as an input port when performing transmission only)

TXD1EN=1

TXD1EN=0, PD3 register PD3_7 bit=0

Serial data output, TXD1SEL=1

Serial data output

Serial data input

TxD

/RxD

(P3

)

TxD

(P0

)

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 198 199

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