
R8C/10 Group
Rev.1.20 Jan 27, 2006 page 107 of 180
REJ09B0019-0120
Figure 14.3 ADCON2 Register and AD Register
14. A/D Converter
A
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
1
)
Symbol Address After reset
ADCON2 00D4
16
00
16
7
6
5
4
3
2
1
0
A
D
c
o
n
v
e
r
s
i
o
n
m
e
t
h
o
d
s
e
l
e
c
t
b
i
t
0
:
W
i
t
h
o
u
t
s
a
m
p
l
e
a
n
d
h
o
l
d
1
:
W
i
t
h
s
a
m
p
l
e
a
n
d
h
o
l
d
B
i
t
s
y
m
b
o
lB
i
t
n
a
m
e Function
R
N
O
T
E
S
:
1
.
I
f
t
h
e
A
D
C
O
N
2
r
e
g
i
s
t
e
r
i
s
r
e
w
r
i
t
t
e
n
d
u
r
i
n
g
A
/
D
c
o
n
v
e
r
s
i
o
n
,
t
h
e
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
W
h
e
n
w
r
i
t
e
,
w
r
i
t
e
“
0
”
.
W
h
e
n
r
e
a
d
,
i
t
s
c
o
n
t
e
n
t
i
s
“
0
”
.
A
D
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sA
f
t
e
r
r
e
s
e
t
A
D 0
0
C
1
1
6
-
0
0
C
0
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
When BITS bit in ADCON1
register is set to “1” (10-bit
mode)
Function
15
7
7
0
0
8
A/D conversion result
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
W
h
e
n
w
r
i
t
e
,
s
e
t
t
o
“
0
”
.
W
h
e
n
r
e
a
d
,
i
t
s
c
o
n
t
e
n
t
i
s
“
0
”
.
When read, its content is
indeterminate.
SMP
000
R
e
s
e
r
v
e
d
b
i
tS
e
t
t
o
“
0
”
(
b
3
-
b
1
)
(
b
7
-
b
4
)
R
R
R
RO
RO
8
l
o
w
-
o
r
d
e
r
b
i
t
s
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
2 high-order bits of A/D
conversion result
When BITS bit in ADCON1
register is set to “0” (8-bit
mode)
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