
R8C/10 Group
Rev.1.20 Jan 27, 2006 page 45 of 180
REJ09B0019-0120
Figure 10.9 Interrupts Priority Select Circuit
Interrupt
request
acce
ted
Highest
Lowest
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Interrupt request level
resolution output signal
Timer Z
Timer
Timer C
Timer
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A
R
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1
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UART0 reception
A/D conversion
UART1 transmission
UART0 transmission
Key input interrupt
I
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I
N
T
3
INT2
I
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1
Priority level of each interrupt
A
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m
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h
Watchdog timer
I
N
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0
Oscillation stop detection
• Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among
those requested.
Figure 10.9 shows the Interrupts Priority Select Circuit.
10.1 Interrupt Overview
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