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PALMiCE3 AUD360 model Hardware Manual Chapter 3 Target Interface Specifications 11
3.2.3 Specifications of AUD interface signals
VIL Target voltage ÷ 2 – 0.35
Input voltage level
VIH Target voltage ÷ 2 + 0.35
VOL Under 0.2V
Output voltage level
VOH Follows the target voltage (1.2V - 3.6V)
*1
*1 : In the case of TRST signal, it will be 1.8V - 5.5V (Follows target)
3.2.4 RSTOUT signal
/RSTOUT signal is a signal for requesting reset from PALMiCE3 to the target system. The signal will be output
by open-collector circuit if from PALMiCE3.
Connect this signal to the reset circuit of the whole target system inclusive of CPU and peripherals. It is required
for synchronization at CSIDE startup.
If connection can not be established, you can still press reset switch button on the target system or use
power-on-reset.
3.2.5 The target interface on PALMiCE3 side
The target interface on PALMiCE3 side is described.
No. Signal Remarks No. Signal Remarks
1 AUDCK2
33Ω Series
2 GND
3 AUDATA0
33Ω Series
4 GND
5 AUDATA1
33Ω Series
6 GND
7 AUDATA2
33Ω Series
8 GND
9 AUDATA3
33Ω Series
10 GND
11 AUDSYNC
33Ω Series
12 GND
13 AUDRST
33Ω Series
14 GND
15 AUDMD
33Ω Series
16 GND
17 TCK
33Ω Series
18 GND
19 TMS
33Ω Series
20 GND
21 TRST
33Ω Series
22
GND
ASEMD
23 TDI
33Ω Series
24 GND
25 TDO
33Ω Series 10KΩ Pull-up
*1
26 GND
27 ASEBRK 33 Series 10K Pull-up
*1
28 GND
29 VCC 100 Series 30 GND
31 RESET 100 Series 100K Pull-down 32 GND
33 SENSE 100 Series 34 GND
35 AUDCK1 33 Series 36 GND
*1 : Potential has been pulled up to the same level as target VCC reference voltage.
Each name of the signal varies depending on the CPU you use.
Besides this manual, also, consult "Technical Information on PALMiCE3" up on our website
(http://www.computex.co.jp/eg/)
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