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THEORY OF OPERATION

This chapter describes the main components of the SPM.

IPMC subsystem

The Intelligent Platform Management Controller (IPMC) subsystem on the SPM comprises the

following:

 Renesas H8S/2168 16-bit single-chip microcontroller running at 32 MHz

 I/O FPGA

 Nonvolatile (NV) memory

The IPMC has the following features:

 Conforms to the PICMG† 3.0 Revision 2.0 AdvancedTCA† Base Specification

 Configurable sensor and I/O interfaces

 Local power input

 Dual redundant I

C management links for IPMB-0

 32 KB of I

C-based nonvolatile storage for FRU records and event logs

 Board power (voltage) control

 Hardware watchdog to provide isolation services and fault recovery of the IPMC controller

Hardware address

The hardware address for the SPM on the ATCA IPMB-0 bus is 0x72 or 0x73, depending on the

shelf slot in which the module is inserted. Address 0x72 corresponds to the module installed in

the RTM slot for the hub with the lower site number. (The actual IPMB address will be 0xE4—

0xE5 or 0xE6—0xE7.)

The address is determined by the SLOT ID inputs. For more information, see Redundancy on

page 18.

NV memory

A 32-KB nonvolatile (NV) memory chip resides on the Renesas H8S/2168 microcontroller I

bus 2. It is used by the system to store application information.

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Renesas H8S/2168 Manual de usuario Pagina 13